Semiconductor device manufacturing involves a lengthy fabrication process that includes multiple patterning operations. Each of the patterning operations utilizes a photolithographic process sequence. The photolithographic process sequence involves coating a wafer with a photosensitive material such as photoresist, then forming a pattern in the photosensitive material. The pattern is formed in the photosensitive material by first exposing the photosensitive material to light that has been directed through a photomask which has an opaque pattern, then developing the photosensitive material to remove the exposed or unexposed portion of the film, depending on whether positive or negative photosensitive material is used. Such a pattern is found at several device levels in the manufacture of a semiconductor device.
These operations are carried out along with several other operations in an integrated lithography tool that typically includes a stepper or scanner within which the exposure operation is carried out, and a track that includes multiple units that perform the previously discussed develop and coat operations as well as hard bake operations, soft bake operations, cooling operations, adhesion enhancement operations, post-exposure bake operations and requisite wafer transfer operations between the stations. There are therefore processing times associated with each of the aforementioned unit operations including wafer-to-wafer transfer times between the unit operations. Moreover, the time required to process an entire lot through a unit operation is influenced by the number of units used to carry out the operation. For example, in a single lithography tool, there may be multiple coating operations, multiple hard bake stations, multiple developer heads, and so forth. When a lot of semiconductor wafers has completed processing at the lithography operation, and a new lot is poised to be processed at the lithography tool, the recticle or photomask must be changed. As such, there are also lot-to-lot set up transfer times to consider.
High volume semiconductor manufacturing facilities typically have several of the aforementioned lithography tools and each of the lithography tools may be used to carry out patterning operations at various different levels for various different technologies and device types. Many process recipes may be used to carry out the patterning operations using the various unit operations described above, and the recipes typically vary by device level. Moreover, the number of unit operations may be different for the various lithography tools in a production facility.
In today's rapidly advancing semiconductor manufacturing industry, the time required to process a semiconductor wafer at any stage such as the patterning operations, is critically important. A reduction in processing time at any particular processing operation produces an increased WPH (wafers per hour) output for the processing tool and this increased manufacturing tool output improves the efficiency of the tool producing a cost savings. Each processing tool such as a lithography tool may typically include an inherently time limiting operation such as the alignment and exposure operation in a lithography tool. It would be inefficient and cost ineffective to have an overall lithography operation limited by a different operation, for example a baking operation that requires more time than the exposure operation due to an insufficient number of bake plates or other process inefficiencies associated with the baking operation. Such would be a bottleneck that hinders overall progress at the lithography operation.
It is therefore critically important to quickly identify bottlenecks in lithography operations. Moreover, it would be advantageous to specify one fabrication parameter such as lithography tool or technology type, device type, device level, or reticle and to be able to quickly compare processing times between other of the fabrication parameters.